1. Field of the Invention
The present invention relates to an overlay key and a method of measuring overlay accuracy using the same, and more particularly, to an overlay key that is used as a mark for precisely aligning two films disposed on different levels of a wafer, and to a method of measuring overlay accuracy between the films disposed on the different levels of the wafer using same.
2. Description of the Related Art
As the integration density of semiconductor devices increases, the size of patterns formed on a wafer are scaled down, and the density of the patterns increases. In particular, the density of patterns in a cell region is much higher than the density of patterns in a peripheral circuit region. Semiconductor devices, disposed in the cell region or the peripheral circuit region, are manufactured by repeating a thin-film forming process which involves depositing and patterning thin films several times.
In the thin-film forming process including photolithography and etch processes, a new film that is patterned in a current step may deviate from a thin film that has been deposited on a wafer in a previous step. Since an extent of deviation, i.e., an overlay accuracy between a current film and a previous film, greatly affects the thin-film forming process, an overlay key is used to measure the overlay accuracy of the films.
Overlay accuracy used to be measured by determining a misalignment with the naked eye using a vernier key. However, nowadays, the overlay accuracy is measured using a box-in-box overlay key, which is far more precise than the conventional vernier key.
Referring to FIG. 1, the box-in-box overlay key comprises a main scale 10 and a vernier scale 20. The vernier scale 20 forming an internal box is enclosed by the main scale 10 forming an external box and having a square plane. FIG. 1 illustrates an example of the box-in-box overlay key in which the main scale 10 is formed of a trench-shaped concave portion and the vernier scale 20 is formed of an island-shaped convex portion.
In the overlay key, a signal is obtained from image information for the overlay key, and a variation in the signal is observed as shown in FIG. 2. FIG. 2 is a waveform diagram of the signal obtained from the image information for the overlay key shown in FIG. 1, which illustrates overlay accuracy of the main scale 10 and the vernier scale 20.
Referring to FIG. 2, first peaks 31a, 31b, 31c, and 31d of a signal 30 were measured at points 10a, 10b, 10c, and 10d of the trench-shaped main scale 10, respectively, where elevation differences occur. Second peaks 32a and 32b are measured at points 20a and 20b of the island-shaped vernier key 20, respectively, where elevation differences occur.
When the conventional box-in-box overlay key is used, the peaks of the signal 30 as shown in FIG. 2 are observed, and a difference in coordinates between the main scale 10 and the vernier scale 20 is obtained to measure the overlay accuracy.
In the overlay key shown in FIG. 1, the width of the main scale is about 20 μm to 35 μm and the width of the vernier scale is about 10 μm.
Highly integrated semiconductor devices have been developed with sub-90-nm design rules. To manufacture the sub-90-nm semiconductor devices, mass production of sub-25-nm fine patterns is required. For this, a scribe line region has increasingly been scaled down.
In the box-in-box overlay key, the main scale can be formed to about 5 μm such that an overlay key formed in a scribe line region is scaled down. However, since a box-shaped vernier scale that is smaller than the main scale is formed within the main scale, it is difficult to form a smaller overlay key. Also, if the vernier scale is too small, reliability of the signal is lowered.
Thus, to control overlay accuracy between fine patterns of highly integrated devices, a new overlay key having a small size and a high accuracy is required.